The majority of my working life has been involved with field programmable gate arrays (FPGAs) in various sales and marketing roles. These have evolved over the past 30 years to be the go-to logic solution for many customers. Designs include the “companion chip” for the field programmable radio frequency (FPRF) devices such as LMS6002D and LMS7002M. An FPGA often provides the control and baseband signal processing elements of the wireless sub-system.
However, the consistent feedback I heard over the years about the FPGA design flow is that the tools are both complex and difficult to use without adequate training. That’s not to say that the tools supplied by the FPGA vendors have not made huge strides, it’s just that the devices and system designs have grown in proportion.
The current tools from vendors such as Altera Corporation, called Quartus II, must be capable of providing a smooth flow all the way from capturing the design intention to generating a configuration file for the final production. This requires specialist skills at every step. Massive engineering efforts have been made to improve and simplify the various stages of the design process, but the customer designs keep getting bigger and faster. At the “front-end”, users can choose from multiple software vendors or open-source packages for the non-architectural aspects such as design capture and simulation. The level of design abstraction has been progressively enhanced to the point where hardware engineers can evaluate architectural options in third party tools, such as ModelSim from Mentor Graphics.
The FPGA vendors develop bespoke algorithms tuned to the individual chip architectures for “back-end” placement and routing of designs during the final implementation stage. The companies recognize that the design tools can be a major differentiation for their product offerings, and strive to provide a high performance automated push-button flow wherever possible.
However, the FPGA companies also appreciate that the tool flow inside Quartus or its equivalents is alien to the software community. There are two key reasons that this is important. Firstly, the latest FPGA device families, such as Cyclone V or Arria 10 feature embedded ARM core processors. Within the design department of many large companies, it is the software team which decides on the choice of processor. Moreover, the second important factor is that there is typically a ratio of between 5:1 and 10:1 in the number of software engineers compared with hardware designers. This division of responsibilities and disparity in engineering talent has been a sharp focus for FPGA vendors over many years.
Today Altera supports the Open Computing Language (OpenCL) software that allows users unprecedented efficiency for creating code. It allows software engineers to work in a way that is both familiar and comfortable. The product provides a methodology for system architects to explore architectural options.
OpenCL allows software programmers to take OpenCL code and rapidly exploit the massively parallel architecture of an FPGA. It enables kernel code to be emulated and debugged, pinpoints performance bottlenecks, and profiles and recompiles to a hardware implementation. The FPGA programmable fabric is used to create hardware accelerated function blocks, leaving the tasks most appropriate to software to run on the embedded cores. The fabric can also be used by designers to create custom peripherals for the processor.
The objective of the Quartus tool suite working with OpenCL, called Altera SDK for OpenCL, is to emulate OpenCL C accelerator code on an x86-based host in seconds and get a detailed optimization report with specific algorithm pipeline dependency information. Users can then prototype the accelerator kernel on a virtual FPGA fabric in minutes, and once satisfied with the system performance, they can progress through the longer compile time to generate a working solution.
Combining the ease-of-use of design tools like OpenCL with the intuitive GUI provided by Lime offers a rapid path to a complete wireless sub-system.